The present invention relates to a data processor adapted for a 1-chip microcomputer.
In a 1-chip microcomputer, a central processing unit or a micro-processing unit is built in together with a read/write memory. The stored contents of the read/write memory is correctly maintained when a power source voltage is a normal value, but if the power source voltage is lowered less than a rated value or the power source is interrupted, an error occurs in the contents or the contents are erased. Therefore, an auxiliary power source for retaining the contents of the memory is additionally provided. FIG. 1 shows one example of a conventional 1-chip microcomputer. In the conventional microcomputer 1, a read/write memory 2 is built in, and is connected through an address bus 3 and a data bus 4 to a micro-processing unit (not shown) provided in a chip. In the memory 2 are provided a read/write inhibit terminal and a power terminal. A D-type latch 5 is connected at the Q output as an inhibit flag to the inhibit terminal. The data bus 4 is coupled to the D input of the latch 5, and a write signal is coupled to the G input of the latch 5. A non-maskable interrupt (NMI) input from a comparator 7 is applied to the interrupt input pin 6 of the chip 1. A reference voltage Vref is applied to the reference input terminal of the comparator 7, and a power voltage V.sub.DD is applied to the comparison input terminal of the comparator 7. The power voltage V.sub.DD is supplied to the power input pin 8 of the chip 1, and a stand-by voltage V.sub.STB is applied through a diode 10 to an auxiliary power input pin 9. The power voltage V.sub.DD is also applied through a diode 11 to the input pin 9. The latch 5 is energized by the auxiliary power voltage V.sub.STB.
The operation of the circuit shown in FIG. 1 will be described with reference to FIG. 2. When the power voltage V.sub.DD is higher than the reference voltage Vref, the output of the comparator 7 is high, and the non-maskable interrupt signal NMI is, as shown in FIG. 2(b), high. When V.sub.DD &lt;Vref occurs at the time t1, the output of the comparator 7 becomes low, and the interrupt signal NMI is applied to the interrupt input pin 6. Since the power voltage V.sub.DD is substantially equal to the Vref immediately after the signal NMI is produced and the chip 1 operates normally, data to be stored in the memory 2 is stored therein. Thereafter, a write inhibit signal is applied, as shown in FIG. 2(c), from the Q output terminal of the latch 5 to the inhibit terminal. The setting operation of the latch 5 is carried out by a software. Since the memory 2 and the latch 5 are energized, even if the power voltage V.sub.DD is lowered, by the stand-by voltage V.sub.STB, the data of the memory 2 and the inhibit output of the latch 5 are normally maintained continuously.
When the power voltage V.sub.DD is recovered and becomes higher than the reference voltage Vref at the time t2, the output of the comparator 7 again becomes high. The chip 1 thus executes a program (software processing) to allow the Q output of the latch 5 to become, as shown in FIG. 2(c), low, and the memory 2 is thus reset to the accessible state. Since the aforementioned conventional memory protecting system, however, performs the protection processing by the program (software) when the power voltage is extraordinarily lowered, following various drawbacks and disadvantages occur.
(a) A non-maskable interrupt must be exclusively prepared so as to inform the abnormal drop of the power voltage V.sub.DD to the micro-processing unit, and an exclusive input pin 6 must be necessarily provided therefor at the chip 1.
(b) Since the data is saved in the memory 2 after V.sub.DD &lt;Vref occurs and the inhibit setting by the latch 5 is carried out, it is necessary to maintain the operation of the micro-processing unit normal only during this period, and a variety of remedies should be necessarily provided so as not to abruptly lower the power voltage V.sub.DD.
(c) Inasmuch as the latch 5 is set by the program or software, when the power voltage V.sub.DD drops lower than the lower normal operation limit value of the micro-processing unit to bring the micro-processing unit into the indefinite state, the latch 5 is reset, and the contents of the memory 2 are feasibly rewritten.
(d) Since the aforementioned non-maskable interrupt processing program is thus necessary, the program area to be used by a user is diminished that much.
(e) It is, of cource, considered to control the latch 5 directly by the NMI signal to the input pin 6, but when this control is performed during the data writing operation, an erroneous data tends to be written in the memory.